Design of Power Reduction in Very Large Scale Integrated Systems

Language: English

Published by LAP LAMBERT Academic Publishing Feb 2024, 2024

6207460421 / 9786207460427

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This item is printed on demand - Print on Demand Titel. Neuware -Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 296 pp. Englisch.

Seller Inventory # 9786207460427

Title
Design of Power Reduction in Very Large Scale Integrated Systems
Author
B. Babu Rajesh
Publisher
LAP LAMBERT Academic Publishing Feb 2024
Publication year
2024
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6207460421
ISBN 13
9786207460427
Item weight
459 grams
Dimensions
220x150x19 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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