Delay Fault Testing for VLSI Circuits

Krstic, Angela;Cheng, Kwang-Ting

ISBN 10: 0792382951 / ISBN 13: 9780792382959

Published by Kluwer Academic Pub, Boston, 1998

About this Item

A very clean, unmarked copy.

Seller Inventory # 00033636

Bibliographic Details

• Title: Delay Fault Testing for VLSI Circuits
• Publisher: Kluwer Academic Pub, Boston
• Publication Date: 1998
• Language: English
• ISBN 10: 0792382951
• ISBN 13: 9780792382959
• Binding: Hardcover
• Edition: First Edition.
• Condition: Very Fine
• Seller catalogs:
  • Computer Studies & Technology

About this title

Synopsis

In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech­ niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

Synopsis

With the ever-increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is further expected to grow with the current design trend of moving towards deep submicron devices. After a long period of prevailing belief that high stuck-at fault coverage is sufficient to guarantee high quality of shipped products, the industry is now forced to rethink other types of testing. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed."Delay Fault Testing for VLSI Circuits" presents a selection of existing delay testing research results. It combines introductory material with state-of-the-art techniques that address some of the current problems in delay testing. "Delay Fault Testing for VLSI Circuits" covers some basic topics such as fault modeling and test application schemes for detecting delay defects. It also presents summaries and conclusions of several recent case studies and experiments related to delay testing.

A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. "Delay Fault Testing for VLSI Circuits" is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires a basic background in digital testing. The book can used as supplementary material for a graduate-level course on VLSI testing.