Cost-effective Methods for High-speed Nanometer CMOS VLSI Design (Paperback)

Language: English

Published by LAP Lambert Academic Publishing, 2025

6208480620 / 9786208480622

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Paperback. The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.…

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Title
Cost-effective Methods for High-speed Nanometer CMOS VLSI Design (Paperback)
Author
Charbel Akl
Publisher
LAP Lambert Academic Publishing
Publication year
2025
Condition
new
Binding
Paperback
Language
English
ISBN 10
6208480620
ISBN 13
9786208480622

CitiRetail

Stevenage, United Kingdom

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AbeBooks seller since June 29, 2022

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