Title: Computer Architecture: From Microprocessors to Supercomputers (The ^AOxford Series in Electrical and Computer Engineering)
Publisher: Oxford University Press
Publication Date: 2005
Language: English
ISBN 10: 019515455X
ISBN 13: 9780195154559
Binding: Hardback
Condition: Good
Weight: 1279 grams

About this title

Synopsis

PART I: sets the stage, provides context, reviews some of the prerequisite topics and gives a taste of what is to come in the rest of the book. Included are two refresher-type chapters on digital circuits and components, a discussion of types of computer systems, an overview of digital computer technology, and a detailed perspective on computer system 3erformance. PART II:lays out the user's interface to computer hardware known as the instruction-set architechture (ISA). For better understanding, the instruction set of MiniMIPS (a simplified, yet very realistic, machine for which open reference material and simulation tools exist) is described. Included is a chapter on variations in ISA (e.g. RISC vs CISC) and associated cost performace tradeoffs. The next two parts cover the central processing unit (CPU). PART III: describes the structure of arithmetic/logic units (ALUs) in some detail. Included are discussions of fixed- and floating-point number representations, design of high-speed adders, shift and logical operations, and hardware multipliers/dividers. Implementation aspects and pitfalls of floating-point arthimetic are also discussed. PART IV: is devoted to data path and control circuits comprising the CPU. Beginning with instruction execution steps, the needed components and control mechanisms are derived. These are followed by an exposition of control design strategies, use of a pipelined data path for performance enhancement, and various limitations of pipelining due to data and control dependencies. PART V: concerned with the memory system. The technologies in use for primary and secondary memories are described, along with their strengths and limitations. It is shown how the use of cache memories effectively bridges the speed gap between CPU and main memory. Similarly, the use of virtual memory to provide the illusion of a vast main memory is explained. PART VI: deals with input/output and interfacing topics. A discussion of I/O device technologies is followed by methods of I/O programming and the roles of buses and links (including standards) in I/O communication and interfacing. Elements of processes and context switching, for exception handling or multireaded computation, are also covered. PART VII: introduces advanced architectures. An overview of performance enhancement strategies, beyond simple pipelining, is presented and examples of applications requiring higher performance are cited. These are followed by design strategies and example architectures based on vector or array proccessing, multiprocessing, and multicomputing.

About the Author

Behrooz Parhami is Professor of Computer Engineering at the University of California, Santa Barbara. He has written several textbooks, including Computer Arithmetic (OUP, 2000), and more than 200 research papers. He is a fellow of both the Institute of Electrical and Electronics Engineers (IEEE) and the British Computer Society (BCS). He is a member of the Association for Computing Machinery (ACM), and a distinguished member of the Informatics Society of Iran, for which he served as a founding member and the first president.

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