Clock Generators for SOC Processors

Language: English

Published by Springer US Nov 2010, 2010

1441954708 / 9781441954701

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This item is printed on demand - it takes 3-4 days longer - Neuware -This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs. 264 pp. Englisch.…

Title
Clock Generators for SOC Processors
Author
Amr Fahim
Publisher
Springer US Nov 2010
Publication year
2010
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
1441954708
ISBN 13
9781441954701
Item weight
406 grams
Dimensions
235x155x15 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

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