Chip design CMOS analog integrated circuit layout design and verification: based on Cadence IC 6.1.7 version 2(Chinese Edition)

ISBN 10: 7111737806 (ISBN 13: 9787111737803)

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Seller: liu xing, Nanjing, JS, Chinaliu xing

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Softcover

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Item description from seller

Language:Chinese.Paperback. Pub Date: 2023-12 Pages: 483 Publisher: Machinery Industry Press This book focuses on the field of CMOS analog integrated circuit layout design. Starting from the basic concepts of layout. design methods and EDA tools. it gradually introduces CMOS analog integrated circuit layout planning. . layout. design to tape-out; it introduces in detail the current mainstream analog integrated circuit layout design and verification tools - Cadence IC 6.1.7 and Siemens EDA Cal.

Seller Inventory # NM009329

Bibliographic details

Title
Chip design CMOS analog integrated circuit layout design and verification: based on Cadence IC 6.1.7 version 2(Chinese Edition)
Author
CHEN CHENG YING . CHEN LI MING . JIANG JIAN HUA . WANG XING HUA
Condition
New
Binding
paperback

liu xing

Nanjing, JS, China

5-star seller

AbeBooks seller since April 7, 2009

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NAN JING SHI JIANG NING QU NING YUAN DIAN ZI SHANG WU ZHONG XIN

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Nanjing, JS China 211100