Cache Memory Book, The, Second Edition (The Morgan Kaufmann Series in Computer Architecture and Design)

Jim Handy

ISBN 10: 0123229804 / ISBN 13: 9780123229809

Published by Morgan Kaufmann Pub, 1998

About this Item

2nd sub edition. 229 pages. 9.50x6.25x0.75 inches. In Stock.

Seller Inventory # __0123229804

Bibliographic Details

• Title: Cache Memory Book, The, Second Edition (The Morgan Kaufmann Series in Computer Architecture and Design)
• Publisher: Morgan Kaufmann Pub
• Publication Date: 1998
• Language: English
• ISBN 10: 0123229804
• ISBN 13: 9780123229809
• Binding: Hardcover
• Edition: 2nd Edition
• Condition: Brand New

About this title

Synopsis

The Second Edition of The Cache Memory Book introduces systems designers to the concepts behind cache design. The book teaches the basic cache concepts and more exotic techniques. It leads readers through someof the most intricate protocols used in complex multiprocessor caches. Written in an accessible, informal style, this text demystifies cache memory design by translating cache concepts and jargon into practical methodologies and real-life examples. It also provides adequate detail to serve as a reference book for ongoing work in cache memory design.
The Second Edition includes an updated and expanded glossary of cache memory terms and buzzwords. The book provides new real world applications of cache memory design and a new chapter on cache"tricks".

• Illustrates detailed example designs of caches
• Provides numerous examples in the form of block diagrams, timing waveforms, state tables, and code traces
• Defines and discusses more than 240 cache specific buzzwords, comparing in detail the relative merits of different design methodologies
• Includes an extensive glossary, complete with clear definitions, synonyms, and references to the appropriate text discussions

About the Author

Jim Handy is a Principal Analyst for memories in Dataquest's Semiconductor group. He is a frequent lecturer and writer on the subject of cache memorydesign and is a patent holder in the cache design field.