Architectural Techniques For Managing Non-volatile Caches

Language: English

Published by LAP LAMBERT Academic Publishing Okt 2013, 2013

3659462535 / 9783659462535

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This item is printed on demand - Print on Demand Titel. Neuware -As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making them a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch.…

Seller Inventory # 9783659462535

Title
Architectural Techniques For Managing Non-volatile Caches
Author
Sparsh Mittal
Publisher
LAP LAMBERT Academic Publishing Okt 2013
Publication year
2013
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659462535
ISBN 13
9783659462535
Item weight
119 grams
Dimensions
220x150x5 mm

buchversandmimpf2000

Emtmannsberg, BAYE, Germany

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