Analysis of Low Power Methodologies for Multiplier

Language: English

Published by LAP LAMBERT Academic Publishing Jan 2023, 2023

6205630400 / 9786205630402

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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Softcover

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This item is printed on demand - it takes 3-4 days longer - Neuware -This research work has found an innovative method of designing as adder which is efficient in operating with low power, smaller area and lower PDP. The proposed design was implemented in a Ripple Carry Adder (RCA) to compare the performance with other methods described in this dissertation. As the contribution of this work is primarily focused on low power and the hierarchical approach, gives knowledge about design strategies, the literature on hierarchical approaches for power optimization were given as literature review. 1 bit full adders like BBL-PT, ULPFA, TGA, TFA, SERF and regular CMOS methods were discussed as past adders along with recent designs by researchers. Though there are various design techniques existing with unique advantages, the circuit level approach has been taken in this research due to the scope for construction of a full custom design. The proposed MOSSI-ULP adder is constructed with the integration of PMOS and NMOS transistors as switches than the familiar logic families. This helps to reduce the application of supply voltage and hence power reduction is possible to obtain Multiplier which consume Low Power. 172 pp. Englisch.…

Seller Inventory # 9786205630402

Title
Analysis of Low Power Methodologies for Multiplier
Author
Vijayakumar Shanmugam
Publisher
LAP LAMBERT Academic Publishing Jan 2023
Publication year
2023
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
6205630400
ISBN 13
9786205630402
Item weight
274 grams
Dimensions
220x150x11 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany