Analysis and Design of a DRAM Cell for Low Leakage : Process Level Techniques for Leakage Reduction

Language: English

Published by LAP LAMBERT Academic Publishing, 2010

3838339436 / 9783838339436

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - In Dynamic Random Access Memory, every cell experiences leakage current which consumes part of the stored charge. As the DRAM cell size is shrinking, the leakage is increasing. To maintain the desired data retention time, the leakage current must be kept within the acceptable limit. So, leakage reduction in memories is a topic of great challenge and interest in researchers. This book presents the analysis and design of a DRAM cell for low leakage. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 m submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures, leakage mechanisms in a DRAM cell and process-level techniques for leakage reduction have been reviewed. Process simulation and device simulation of DRAM cell have been done using the ATHENA/ATLAS packages of SILVACO. This book will help the beginners as the book reviews the previous work done by many researchers and provides the trends in DRAM cell designs, theoretical knowledge of leakage mechanisms in DRAM cell and process/device simulation of DRAM cell. …

Seller Inventory # 9783838339436

Title
Analysis and Design of a DRAM Cell for Low Leakage : Process Level Techniques for Leakage Reduction
Author
Rashmi Singh
Publisher
LAP LAMBERT Academic Publishing
Publication year
2010
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3838339436
ISBN 13
9783838339436
Item weight
102 grams
Dimensions
220x150x4 mm

AHA-BUCH GmbH

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