Analysis and Design of CMOS Clocking Circuits For Low Phase Noise
Language: English
Published by Institution of Engineering and Technology, 2020
- Hardcover
- New
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Seller Inventory # L1-9781785618017
- Title
- Analysis and Design of CMOS Clocking Circuits For Low Phase Noise
- Author
- Bae, Woorham; Jeong, Deog-Kyoon
- Publisher
- Institution of Engineering and Technology
- Publication year
- 2020
- Condition
- New
- Binding
- HRD
- Language
- English
- ISBN 10
- 1785618016
- ISBN 13
- 9781785618017
- Item weight
- 642 grams
As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends.
The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.
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About the Author
Woorham Bae received the B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, Korea, in 2010 and 2016, respectively. In 2016, he was with the Inter-University Semiconductor Research Center, Seoul National University, Seoul, Korea. From 2017 to 2019, he was with the University of California, Berkeley, CA, as a Postdoctoral Researcher. He is currently a Senior SerDes Engineer with Ayar Labs, Santa Clara, CA. His current research interests include integrated circuits for silicon photonics, high-speed I/O circuits and architectures, nonvolatile memory systems, and agile hardware design methodology. Dr. Bae received the IEEE Circuits and Systems Society Outstanding Young Author Award in 2018, the Distinguished Ph.D. Dissertation Award from the Department of Electrical and Computer Engineering, Seoul National University in 2016, the IEEE Circuits and Systems Society Pre-Doctoral Scholarship in 2016, and the IEEE Solid-State Circuits Society STG Award in 2015.
Deog-Kyoon Jeong received the B.S. and M.S. degrees in Electronics Engineering from Seoul National University, Seoul, South Korea, in 1981 and 1984, respectively, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California at Berkeley, Berkeley, CA, USA, in 1989. From 1989 to 1991, he was a member of the Technical Staff with Texas Instruments, Dallas, TX, USA. He worked on the modeling and design of BiCMOS gates and the single-chip implementation of the SPARC architecture. Then, he joined the faculty of the Department of Electronics Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, where he is currently an Endowed-Chair Professor. He was one of cofounders of Silicon Image, Sunnyvale, CA, now Lattice Semiconductor, which specialized in digital interface circuits for video displays such as DVI and HDMI. His main research interests include the design of high-speed I/O circuits, phase-locked loops, and memory system architecture. Dr. Jeong was a recipient of the ISSCC Takuo Sugano Award in 2005 for Outstanding Far-East Paper. He is a Fellow of the IEEE.
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