Paperback. Pub Date: 2005 Pages: 710 Language: Chinese in Publisher: Electronic Industry Press book explained by a large number of complete instances the use VerilogHDL VLSI design structured modeling method. key steps and design verification method and other useful content. The book is divided into 11 chapters. covering modeling. structural balance. functional verification. fault simulation. and logic synthesis. and other key issues. as well as after the comprehensive design validation. timing analysis and design for testability content. Sense of book structure is clear and reasonable. content organization. suitable for computer electronics professional senior undergraduate students or graduate courses. also common to the learning VerilogHDL modern IC design flow cite professionals. Contents: Chapter 1 Introduction to digital design methods 1.1 Design Methodology 1.1.1 Desi...

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