SystemVerilog for Hardware Description: RTL Design and Verification - Hardcover

Taraate, Vaibbhav

 
9789811544040: SystemVerilog for Hardware Description: RTL Design and Verification
Hardcover
ISBN 10: 9811544042 ISBN 13: 9789811544040
Publisher: Springer, 2020

Synopsis

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.


"synopsis" may belong to another edition of this title.

About the Author

Vaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.


From the Back Cover

This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.

"About this title" may belong to another edition of this title.

Publisher
Springer
Publication date
2020
Language
English
ISBN 10 
9811544042
ISBN 13 
9789811544040
Binding
Hardcover
Edition number
1
Number of pages
273

Other Popular Editions of the Same Title

9789811544071: SystemVerilog for Hardware Description: RTL Design and Verification

Featured Edition

ISBN 10:  9811544077 ISBN 13:  9789811544071
Publisher: Springer, 2021
Softcover