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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test: 40 (Frontiers in Electronic Testing, 40) - Softcover
Synopsis
This book covers a broad range of topics related to SRAM design and testing. It includes everything from SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing.
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About the Author
Prof. Sachdev has authored several successful books with Springer
From the Back Cover
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.
Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing, 40)
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Gives a process-aware perspective on SRAM circuit design and testProvides detailed coverage of SRAM cell stability, stability sensitivity and analytical evaluation of Static Noise MarginIntroduces the concept of stability fault modelling. Seller Inventory # 5821690
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing, 40)
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Cmos Sram Circuit Design and Parametric Test in Nano-scaled Technologies : Process-aware Sram Design and Test
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
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Springer Netherlands Okt 2010, 2010
ISBN 10: 904817855X
ISBN 13: 9789048178551
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. 212 pp. Englisch. Seller Inventory # 9789048178551
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies : Process-Aware SRAM Design and Test
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. Seller Inventory # 9789048178551
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Paperback)
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Paperback. Condition: new. Paperback. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9789048178551
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
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Springer Netherlands, Springer Netherlands Okt 2010, 2010
ISBN 10: 904817855X
ISBN 13: 9789048178551
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Taschenbuch. Condition: Neu. Neuware -CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 212 pp. Englisch. Seller Inventory # 9789048178551
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Cmos Sram Circuit Design and Parametric Test in Nano-scaled Technologies : Process-aware Sram Design and Test
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Frontiers in Electronic Testing, 40)
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