Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms - Softcover

Ma, Zhe; Marchal, Pol; Scarpazza, Daniele Paolo; Yang, Peng; Wong, Chun; Gómez, José Ignacio; Himpe, Stefaan; Ykman-Couvreur, Chantal; Catthoor, Francky

Softcover

ISBN 10: 9048176107 ISBN 13: 9789048176106

Publisher: Springer, 2010

Synopsis

The main intention of this book is to give an impression of the state of the art in energy-aware task-scheduling-related issues for very dynamic emb- ded real-time processing applications. The material is based on research at IMEC in this area in the period 1999–2006, with a very extensive state-- the-art overview. It can be viewed as a follow-up of the earlier “Modeling, veri?cation and exploration of task-level concurrency in real-time embedded systems” book [234] that was published in 1999 based on the task-level m- eling work at IMEC. In order to deal with the stringent timing requirements, the cost-sensitivity and the dynamic characteristics of our target domain, we have again adopted a target architecture style (i. e. , heterogeneous mul- processor) and a systematic methodology to make the exploration and op- mization of such systems feasible. But this time our focus is mainly on p- viding practical work ?ow out of the (abstract) general ?ow from previous book and also the relevant scheduling techniques for each step of this ?ow. Our approach is very heavily application-driven which is illustrated by several realistic demonstrators. Moreover, the book addresses only the steps above the traditional real-time operating systems (RTOS), which are mainly focused on correct solutions for dispatching tasks. Our methodology is nearly fully independent of the implementations in the RTOS so it is va- able for the realization on those existing embedded systems where legacy applications and underlying RTOS have been developed.

About this title

About the Author

Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer.

From the Back Cover

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platforms gives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications.

Many of these applications are concurrent in the sense that multiple subsystems can be running simultaneously. Also, these applications are so dynamic at run-time that the designs based on the worst case execution times are inefficient in terms of resource allocation (e.g., energy budgets). A novel systematical approach is clearly necessary in the area of system-level design for the embedded systems where those concurrent and dynamic applications are mapped. This material is mainly based on research at IMEC and its international university network partners in this area in the period 1997-2006. In order to deal with the concurrent and dynamic behaviors in an energy-performance optimal way, we have adopted a hierarchical system model (i.e., the gray-box model) that can both exhibit the sufficient detail of the applications for design-time analysis and hide unnecessary detail for a low-overhead run-time management. We have also developed a well-balanced design-time/run-time combined task scheduling methodology to explore the trade-off space at design-time and efficiently handle the system adaptations at run-time. Moreover, we have identified the connection between task-level memory/communication management and task scheduling and illustrated how to perform the task-level memory/communication management in order to obtain the design constraints that enable the this connection. A fast approach is also shown to estimate at the system-level, the energy and performance characterization of applications executing on the target platform processors.

Edition details

• Publisher: Springer
• Publication date: 2010
• ISBN 10: 9048176107
• ISBN 13: 9789048176106
• Binding: Paperback
• Language: English
• Number of pages: 276