Language:Chinese.Soft cover.publisher:Tsinghua University Press Pub. Date :2007-06-01.description:Paperback. Pages Number: 237 Publisher: Tsinghua University Press Pub. Date :2007-06-01. This book describes the 2 ASIC chip using Synopsys tools for synthesis. physical synthesis. formal verification and static timing analysis of the latest concepts
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Destination, rates & speedsSeller: ReadCNBook, Nanjing, JS, China
paperback. Condition: New. Language:Chinese.Paperback. Pages Number: 237 Publisher: Tsinghua University Press Pub. Date :2007-06-01. This book describes the 2 ASIC chip using Synopsys tools for synthesis. physical synthesis. formal verification and static timing analysis of the latest concepts and technologies. but for VDSM (UDSM) process of the complete ASIC design flow design methods are discussed in depth. This book focuses on the use of Synopsys tools to solve the problem of the practical application of various VDS. Seller Inventory # 846231
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Seller: liu xing, Nanjing, JS, China
Soft cover. Condition: New. Language:Chinese.Author:BA TE NA GE ER (Bhatnagar H.) ZHANG WEN JUN YI.Binding:Soft cover.Publisher:Tsinghua University Press Pub. Date :2007-06-01. Seller Inventory # 846231
Quantity: 3 available