Items related to Design of RISC V Five Stage Processor Using Verilog

Design of RISC V Five Stage Processor Using Verilog - Softcover

S, Darshan; K, Jagan; S, Darshini

 
9786209823183: Design of RISC V Five Stage Processor Using Verilog
Softcover
ISBN 10: 6209823181 ISBN 13: 9786209823183
Publisher: LAP Lambert Academic Publishing, 2026

Synopsis

This project presents the design and simulation of a RISC-V 5-stage pipelined processor based on the Reduced Instruction Set Computing (RISC) architecture. The processor operates through five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB), enabling instruction-level parallelism and improved performance. The design is implemented using Verilog HDL and includes key modules such as the Program Counter, Instruction Memory, Register File, Immediate Generator, ALU, Data Memory, Pipeline Registers, and Control Unit. The ALU Control Unit interprets funct3 and funct7 fields to generate required operations, while the main controller ensures proper control signal flow. Hazard detection and data forwarding units are incorporated to handle pipeline hazards effectively. Functional verification using testbench simulations confirms correct instruction execution and register updates. This modular design supports scalability, with future enhancements including branch prediction, cache integration, and FPGA-based real-time implementation.

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Publisher
LAP Lambert Academic Publishing
Publication date
2026
Language
English
ISBN 10 
6209823181
ISBN 13 
9786209823183
Binding
Paperback
Number of pages
56