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Synopsis
In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for this design.
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- PublisherLAP LAMBERT Academic Publishing
- Publication date2020
- ISBN 10 6202797320
- ISBN 13 9786202797320
- BindingPaperback
- LanguageEnglish
- Number of pages80
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VLSI IMPLEMENTATION OF AES ALGORITHM
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LAP LAMBERT Academic Publishing Aug 2020, 2020
ISBN 10: 6202797320
ISBN 13: 9786202797320
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for this design. 80 pp. Englisch. Seller Inventory # 9786202797320
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VLSI IMPLEMENTATION OF AES ALGORITHM
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 6202797320
ISBN 13: 9786202797320
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Taschenbuch
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for this design. Seller Inventory # 9786202797320
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VLSI IMPLEMENTATION OF AES ALGORITHM
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ISBN 13: 9786202797320
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VLSI IMPLEMENTATION OF AES ALGORITHM
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ISBN 13: 9786202797320
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VLSI IMPLEMENTATION OF AES ALGORITHM
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ISBN 10: 6202797320
ISBN 13: 9786202797320
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