Items related to Improved performance of on-chip data interconnects
Synopsis
Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased.
"synopsis" may belong to another edition of this title.
Search results for Improved performance of on-chip data interconnects
Seller Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing Jun 2020, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased. 156 pp. Englisch. Seller Inventory # 9786202672481
Stock Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Softcover
Seller: Books Puddle, New York, NY, U.S.A.
Seller rating 4 out of 5 stars
Condition: New. Seller Inventory # 26387508972
Seller Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Kartoniert / Broschiert
Seller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Kartoniert / Broschiert. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Maddiraala ChennakesavuluHe has completed B.Tech in ECE from JNTUH in 2003, M.Tech in Embedded Systems from JNTUA in 2010. He has completed Ph.D from JNTUA in 2020. He has 16 years of teaching experience and published 20+ national an. Seller Inventory # 387523385
Buy New
£ 44.72
£ 41.99 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Stock Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Softcover
Seller: Majestic Books, Hounslow, United Kingdom
Seller rating 4 out of 5 stars
Condition: New. Print on Demand. Seller Inventory # 393172275
Buy New
£ 83.28
£ 6.50 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 4 available
Stock Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Softcover
Seller: Biblios, Frankfurt am main, HESSE, Germany
Seller rating 4 out of 5 stars
Condition: New. PRINT ON DEMAND. Seller Inventory # 18387508966
Seller Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing Jun 2020, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 156 pp. Englisch. Seller Inventory # 9786202672481
Seller Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Taschenbuch
Seller: preigu, Osnabrück, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Improved performance of on-chip data interconnects | Chennakesavulu Maddiraala (u. a.) | Taschenbuch | 156 S. | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202672481 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Seller Inventory # 118757129
Seller Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply voltage, operating clock frequency, load capacitance and switching activity. All the parameters which influence the dynamic power dissipation are technology dependent except switching activity. Dynamic power dissipation has been reduced by reducing the switching activity. The switching activity has been reduced by adopting a data encoding technique on data interconnects. Encoding the data on it interconnects the promising technique to decrease the dynamic power dissipation and total on-chip delay on the buses and hence overall system performance can be increased. Seller Inventory # 9786202672481
Stock Image
Improved performance of on-chip data interconnects
Published by
LAP LAMBERT Academic Publishing, 2020
ISBN 10: 620267248X
ISBN 13: 9786202672481
New
paperback
Seller: Mispah books, Redhill, SURRE, United Kingdom
Seller rating 4 out of 5 stars
paperback. Condition: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book. Seller Inventory # ERICA823620267248X6