Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the "Power Wall". Even today, this "Power Wall" is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce "Power-Tokens", to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget.
"synopsis" may belong to another edition of this title.
Juan Manuel Cebrián (right) was born in Albacete, Spain, in 1982. Got his B.Sc in Computer Engineering on July 2006, M.Sc in July 2007 and finished his Ph.D on September 2011 (University of Murcia) with the qualification of Summa Cum Laude. His research interests lay in the field of Computer Architecture, particularly in energy efficient designs.
"About this title" may belong to another edition of this title.
Seller: moluna, Greven, Germany
Condition: New. Seller Inventory # 5521910
Quantity: Over 20 available
Seller: AHA-BUCH GmbH, Einbeck, Germany
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the 'Power Wall'. Even today, this 'Power Wall' is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce 'Power-Tokens', to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget. Seller Inventory # 9783848434565
Seller: Mispah books, Redhill, SURRE, United Kingdom
Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book. Seller Inventory # ERICA79638484345636
Quantity: 1 available