Synopsis
Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.
"synopsis" may belong to another edition of this title.
About the Author
Deepa Sinha,M.Tech. :Completed M.Tech.(VLSI Design) degree from MITS (Deemed University)in 2011. Currently working as an Assistant Professor at Jayoti Vidyapeeth Women’s University, Jaipur, INDIA.
"About this title" may belong to another edition of this title.
Search results for Design and Analysis of High Performance Full Adder...
Seller Image
Design and Analysis of High Performance Full Adder Cell
Published by
LAP LAMBERT Academic Publishing Dez 2011, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field. 76 pp. Englisch. Seller Inventory # 9783847310303
Seller Image
Design and Analysis of High Performance Full Adder Cell
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
New
Softcover
Seller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 5509173
Buy New
£ 36.62
£ 42.43 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Seller Image
Design and Analysis of High Performance Full Adder Cell
Published by
LAP LAMBERT Academic Publishing Dez 2011, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 76 pp. Englisch. Seller Inventory # 9783847310303
Seller Image
Design and Analysis of High Performance Full Adder Cell : A Low Power Approach
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field. Seller Inventory # 9783847310303
Seller Image
Design and Analysis of High Performance Full Adder Cell | A Low Power Approach
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
New
Taschenbuch
Seller: preigu, Osnabrück, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Design and Analysis of High Performance Full Adder Cell | A Low Power Approach | Deepa Sinha (u. a.) | Taschenbuch | 76 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783847310303 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 106693460
Stock Image
Design and Analysis of High Performance Full Adder Cell: A Low Power Approach
Published by
LAP LAMBERT Academic Publishing, 2011
ISBN 10: 3847310305
ISBN 13: 9783847310303
Used
Paperback
Seller: Mispah books, Redhill, SURRE, United Kingdom
Seller rating 4 out of 5 stars
Paperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book. Seller Inventory # ERICA75838473103056
Buy Used
£ 137
£ 25 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 1 available