Approaches for Hardware Fault Mitigation in Multicore Processors: Resilient systems with unreliable devices - Softcover

Sánchez, Daniel

Softcover

ISBN 10: 3846554634 ISBN 13: 9783846554630

Publisher: LAP LAMBERT Academic Publishing, 2011

Synopsis

This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.

About this title

About the Author

Daniel Sánchez received his Ms and PhD degrees from the Universidad de Murcia (Spain) in 2007 and 2011, respectively. In 2011, he joined the Intel-UPC Barcelona Research Center as a research scientist. His mainresearch interests include processor microarchitecture, hardware reliability and other topics in the area of resiliency.

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2011
• Language: English
• ISBN 10: 3846554634
• ISBN 13: 9783846554630
• Binding: Paperback
• Number of pages: 192