Most of the research in digital multipliers in the last few decades has focused on reducing the delay of partial products accumulation. In the era of pervasive computing, however, the emphasis of VLSI design is on both high speed and low power operation. This book has presented several new insights into the high speed and energy-efficient redundant binary (RB) multipliers. Advances in the architectural innovation have been made over previous RB multiplier architectures. A structural approach has also been proposed to analyze the performance of N×N-bit RB multiplier constructed with a conglomerate of redundant binary partial products generation, encoding, reduction and conversion methods. Based on this analysis, the RB multiplier design space can be further enlarged through the informed decisions of the relative merits and tradeoffs of these architectural options.
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Associate Professor in the University of Electronic Science and Technology of China. She received the Ph.D from the Nanyang Technological University, Singapore, and has been with the Institute of Microelectronics, Singapore and STMicroelectronics. Her research interests include computer arithmetic circuits and low-power IC design.
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Most of the research in digital multipliers in the last few decades has focused on reducing the delay of partial products accumulation. In the era of pervasive computing, however, the emphasis of VLSI design is on both high speed and low power operation. This book has presented several new insights into the high speed and energy-efficient redundant binary (RB) multipliers. Advances in the architectural innovation have been made over previous RB multiplier architectures. A structural approach has also been proposed to analyze the performance of N×N-bit RB multiplier constructed with a conglomerate of redundant binary partial products generation, encoding, reduction and conversion methods. Based on this analysis, the RB multiplier design space can be further enlarged through the informed decisions of the relative merits and tradeoffs of these architectural options. 172 pp. Englisch. Seller Inventory # 9783838379180
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Taschenbuch. Condition: Neu. Redundant Binary Booth Multipliers | Algorithm, Design, Analysis | Yajuan He | Taschenbuch | 172 S. | Englisch | 2010 | LAP LAMBERT Academic Publishing | EAN 9783838379180 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 107467559
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Most of the research in digital multipliers in the last few decades has focused on reducing the delay of partial products accumulation. In the era of pervasive computing, however, the emphasis of VLSI design is on both high speed and low power operation. This book has presented several new insights into the high speed and energy-efficient redundant binary (RB) multipliers. Advances in the architectural innovation have been made over previous RB multiplier architectures. A structural approach has also been proposed to analyze the performance of N×N-bit RB multiplier constructed with a conglomerate of redundant binary partial products generation, encoding, reduction and conversion methods. Based on this analysis, the RB multiplier design space can be further enlarged through the informed decisions of the relative merits and tradeoffs of these architectural options.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 172 pp. Englisch. Seller Inventory # 9783838379180
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