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Synopsis
Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits.
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Celator
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LAP LAMBERT Academic Publishing Dez 2009, 2009
ISBN 10: 3838334884
ISBN 13: 9783838334882
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits. 108 pp. Englisch. Seller Inventory # 9783838334882
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Celator
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LAP Lambert Academic Publishing, 2009
ISBN 10: 3838334884
ISBN 13: 9783838334882
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Ce. Seller Inventory # 5414065
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Celator
Published by
LAP LAMBERT Academic Publishing Dez 2009, 2009
ISBN 10: 3838334884
ISBN 13: 9783838334882
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 108 pp. Englisch. Seller Inventory # 9783838334882
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Celator : Design and development of a reconfigurable cryptographic co-processor
Published by
LAP LAMBERT Academic Publishing, 2010
ISBN 10: 3838334884
ISBN 13: 9783838334882
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Seller: AHA-BUCH GmbH, Einbeck, Germany
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits. Seller Inventory # 9783838334882
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Celator: Design and development of a reconfigurable cryptographic co-processor
Published by
LAP Lambert Academic Publishing, 2010
ISBN 10: 3838334884
ISBN 13: 9783838334882
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