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Configurable Cache Tuning: A Methodology to Explore Memory Hierarchy Architectures for Embedded Systems - Softcover
Synopsis
In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics are dependent on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, this book presents a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique.
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Configurable Cache Tuning
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LAP LAMBERT Academic Publishing Sep 2010, 2010
ISBN 10: 3838330455
ISBN 13: 9783838330457
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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics are dependent on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, this book presents a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique. 128 pp. Englisch. Seller Inventory # 9783838330457
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Configurable Cache Tuning
Published by
LAP LAMBERT Academic Publishing, 2010
ISBN 10: 3838330455
ISBN 13: 9783838330457
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Softcover
Seller: moluna, Greven, Germany
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Viana PabloPablo Viana is a Professor of Computer Science at the Federal University of Alagoas. He received a M.S. and Ph.D. degrees from the Federal University of Pernambuco in 2002 and 2006, respectively. His interests are in the a. Seller Inventory # 5413653
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Configurable Cache Tuning : A Methodology to Explore Memory Hierarchy Architectures for Embedded Systems
Published by
LAP LAMBERT Academic Publishing, 2009
ISBN 10: 3838330455
ISBN 13: 9783838330457
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics are dependent on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, this book presents a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique. Seller Inventory # 9783838330457
Seller Image
Configurable Cache Tuning
Published by
LAP LAMBERT Academic Publishing Sep 2010, 2010
ISBN 10: 3838330455
ISBN 13: 9783838330457
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In platform tuning, memory hierarchy is an important element to be optimized. Many cache configurations need to be evaluated in order to find out the best choice in terms of performance, silicon area, or power consumption to an application. Most models to estimate those metrics are dependent on the cache size parameters and their respective miss rate. Instead of using traditional simulation tools to estimate cache miss rate through several cache simulations, this book presents a simplified yet efficient technique to estimate the miss rate of many different cache configurations in just one single-pass simulation. The approach basically proposes the generation of locality and conflict tables, which reflects the addressing behavior properties of the application. The proposed technique intends to make the miss estimation easier and the cache exploration faster. Since the table structure is plainly based on elementary bitwise operations of comparison and shifting, flexible software-based approaches can be considered to implement the proposed technique.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 128 pp. Englisch. Seller Inventory # 9783838330457