Items related to Testing Chips with Mesh-Based Network-on-Chip
Synopsis
Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.
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About the Author
Alexandre received the degree of Ph.D. in Computer Science from the UFRGS University, Brazil, in 2007. Marcelo received the degree of Ph.D. in Electrical Engineer from INPG, France, in 1994. Fernando received the degree of Ph.D. in Electrical Engineer from LIRMM, France, in 1994.
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Testing Chips with Mesh-Based Network-on-Chip
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead. 172 pp. Englisch. Seller Inventory # 9783838321615
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Testing Chips with Mesh-Based Network-on-Chip
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which co. Seller Inventory # 5412824
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Testing Chips with Mesh-Based Network-on-Chip
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Taschenbuch. Condition: Neu. Testing Chips with Mesh-Based Network-on-Chip | Alexandre Amory (u. a.) | Taschenbuch | 172 S. | Englisch | 2009 | LAP LAMBERT Academic Publishing | EAN 9783838321615 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 101444591
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Testing Chips with Mesh-Based Network-on-Chip
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 172 pp. Englisch. Seller Inventory # 9783838321615
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Testing Chips with Mesh-Based Network-on-Chip
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ISBN 13: 9783838321615
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead. Seller Inventory # 9783838321615
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Testing Chips with Mesh-Based Network-on-Chip
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