Synopsis
1 Introduction.- 2 Basics.- 3 A Sequential DLX Design.- 4 Basic Pipelining.- 5 Interrupt Handling.- 6 Memory System Design.- 7 IEEE Floating Point Standard and Theory of Rounding.- 8 Floating Point Algorithms and Data Paths.- 9 Pipelined DLX Machine with Floating Point Core.- A DLX Instruction Set Architecture.- A.1 DLX Fixed-Point Core: FXU.- A.1.1 Instruction Formats.- A.1.2 Instruction Set Coding.- A.2 Floating-Point Extension.- A.2.1 FPU Register Set.- A.2.2 FPU Instruction Set.- B Specification of the FDLX Design.- B.1 RTL Instructions of the FDLX.- B.1.l Stage IF.- B.1.2 Stage ID.- B.1.3 Stage EX.- B.1.4 Stage M.- B.1.5 Stage WB.- B.2 Control Automata of the FDLX Design.- B.2.1 Automaton Controlling Stage ID.- B.2.2 Precomputed Control.
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