Synopsis
In this work The novel single ended 5T and 6T SRAM cell is presented. This transistor is high density cell or takes less area than conventional 6T SRAM cell. Leakage current of this cell is very low as compared to other 5T or conventional 6T cell. There is a requirement of precharge circuit for this cell as that in conventional 6T SRAM cell. This cell is also power efficient. Also results show that the data stored in this cell is highly stable.There is always scope of improvement in any type of circuit or application. With the proposed configuration we can improve it with various techniques. We can change aspect ratio of the cell for better results. We can apply clock gating for power efficient circuit. We can improve peripheral circuit for better performance.
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About the Author
Rohin Gupta is research scholar at GNDEC,Ludhiana and chairman of Brainiac Solutions firm (www.brainiacsolutions.in). Professor Sandeep Singh Gill is working as Professor and Head in ECE Department at GNDEC, Ludhiana.Navneet Kaur is working as Assistant Professor at GNDEC, Ludhiana.
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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LAP LAMBERT Academic Publishing Apr 2016, 2016
ISBN 10: 3659861111
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this work The novel single ended 5T and 6T SRAM cell is presented. This transistor is high density cell or takes less area than conventional 6T SRAM cell. Leakage current of this cell is very low as compared to other 5T or conventional 6T cell. There is a requirement of precharge circuit for this cell as that in conventional 6T SRAM cell. This cell is also power efficient. Also results show that the data stored in this cell is highly stable.There is always scope of improvement in any type of circuit or application. With the proposed configuration we can improve it with various techniques. We can change aspect ratio of the cell for better results. We can apply clock gating for power efficient circuit. We can improve peripheral circuit for better performance. 108 pp. Englisch. Seller Inventory # 9783659861116
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Gupta RohinRohin Gupta is research scholar at GNDEC,Ludhiana and chairman of Brainiac Solutions firm (www.brainiacsolutions.in). Professor Sandeep Singh Gill is working as Professor and Head in ECE Department at GNDEC, Ludhiana.Navne. Seller Inventory # 158877267
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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LAP LAMBERT Academic Publishing, 2016
ISBN 10: 3659861111
ISBN 13: 9783659861116
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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LAP LAMBERT Academic Publishing Apr 2016, 2016
ISBN 10: 3659861111
ISBN 13: 9783659861116
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In this work The novel single ended 5T and 6T SRAM cell is presented. This transistor is high density cell or takes less area than conventional 6T SRAM cell. Leakage current of this cell is very low as compared to other 5T or conventional 6T cell. There is a requirement of precharge circuit for this cell as that in conventional 6T SRAM cell. This cell is also power efficient. Also results show that the data stored in this cell is highly stable.There is always scope of improvement in any type of circuit or application. With the proposed configuration we can improve it with various techniques. We can change aspect ratio of the cell for better results. We can apply clock gating for power efficient circuit. We can improve peripheral circuit for better performance.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 108 pp. Englisch. Seller Inventory # 9783659861116
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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LAP LAMBERT Academic Publishing, 2016
ISBN 10: 3659861111
ISBN 13: 9783659861116
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this work The novel single ended 5T and 6T SRAM cell is presented. This transistor is high density cell or takes less area than conventional 6T SRAM cell. Leakage current of this cell is very low as compared to other 5T or conventional 6T cell. There is a requirement of precharge circuit for this cell as that in conventional 6T SRAM cell. This cell is also power efficient. Also results show that the data stored in this cell is highly stable.There is always scope of improvement in any type of circuit or application. With the proposed configuration we can improve it with various techniques. We can change aspect ratio of the cell for better results. We can apply clock gating for power efficient circuit. We can improve peripheral circuit for better performance. Seller Inventory # 9783659861116
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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LAP LAMBERT Academic Publishing, 2016
ISBN 10: 3659861111
ISBN 13: 9783659861116
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Taschenbuch. Condition: Neu. CMOS SRAM Design and analysis of low leakage and high speed SRAM cell | Rohin Gupta (u. a.) | Taschenbuch | 108 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659861116 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 103822325
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CMOS SRAM Design and analysis of low leakage and high speed SRAM cell
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