Simple Processors for Executing Scalar/Vector/ Matrix Instructions: Design, Implementation, and Performance Evaluation - Softcover
Synopsis
Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS).
"synopsis" may belong to another edition of this title.
About the Author
Elsayed A. Elsayed is an assistant lecturer at Faculty of Engineering, Aswan University, Egypt. He received his master degree in Computer Science and Engineering in 2014. He is interested in computer architecture, parallel processing, vector/matrix processing, multi/many-core, and VHDL/FPGA implementations.
"About this title" may belong to another edition of this title.
Search results for Simple Processors for Executing Scalar/Vector/ Matrix...
Seller Image
Simple Processors for Executing Scalar/Vector/ Matrix Instructions
Published by
LAP LAMBERT Academic Publishing Feb 2016, 2016
ISBN 10: 365983226X
ISBN 13: 9783659832260
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS). 224 pp. Englisch. Seller Inventory # 9783659832260
Seller Image
Simple Processors for Executing Scalar/Vector/ Matrix Instructions
Published by
LAP LAMBERT Academic Publishing, 2016
ISBN 10: 365983226X
ISBN 13: 9783659832260
New
Softcover
Seller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Elsayed ElsayedElsayed A. Elsayed is an assistant lecturer at Faculty of Engineering, Aswan University, Egypt. He received his master degree in Computer Science and Engineering in 2014. He is interested in computer architecture, para. Seller Inventory # 158877094
Buy New
£ 54.93
£ 42.23 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Seller Image
Simple Processors for Executing Scalar/Vector/ Matrix Instructions | Design, Implementation, and Performance Evaluation
Published by
LAP LAMBERT Academic Publishing, 2016
ISBN 10: 365983226X
ISBN 13: 9783659832260
New
Taschenbuch
Seller: preigu, Osnabrück, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Simple Processors for Executing Scalar/Vector/ Matrix Instructions | Design, Implementation, and Performance Evaluation | Elsayed Elsayed (u. a.) | Taschenbuch | 224 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659832260 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. Seller Inventory # 103942908
Seller Image
Simple Processors for Executing Scalar/Vector/ Matrix Instructions
Published by
LAP LAMBERT Academic Publishing Feb 2016, 2016
ISBN 10: 365983226X
ISBN 13: 9783659832260
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS).VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 224 pp. Englisch. Seller Inventory # 9783659832260
Seller Image
Simple Processors for Executing Scalar/Vector/ Matrix Instructions : Design, Implementation, and Performance Evaluation
Published by
LAP LAMBERT Academic Publishing, 2016
ISBN 10: 365983226X
ISBN 13: 9783659832260
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS). Seller Inventory # 9783659832260