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Synopsis
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques.
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About the Author
Nurbaizura Bt Ramji is a bachelor in Electronic Engineering (Telecommunications) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is Research Scientist at UNIMAS.
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Performance Optimization in Network-on-Chip (NoC) Architecture
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LAP LAMBERT Academic Publishing Feb 2014, 2014
ISBN 10: 3659523356
ISBN 13: 9783659523359
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques. 88 pp. Englisch. Seller Inventory # 9783659523359
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Performance Optimization in Network-On-Chip (Noc) Architecture
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VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2014
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Performance Optimization in Network-On-Chip (Noc) Architecture
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VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2014
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Condition: New. Print on Demand pp. 88 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam. Seller Inventory # 132829310
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Performance Optimization in Network-On-Chip (Noc) Architecture
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VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2014
ISBN 10: 3659523356
ISBN 13: 9783659523359
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Performance Optimization in Network-on-Chip (NoC) Architecture
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Ramji NurbaizuraNurbaizura Bt Ramji is a bachelor in Electronic Engineering (Telecommunications) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is Research Scientist at UNIMAS.The escalating complexity of System-on-Chips (. Seller Inventory # 5162278
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Performance Optimization in Network-on-Chip (NoC) Architecture
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LAP LAMBERT Academic Publishing Feb 2014, 2014
ISBN 10: 3659523356
ISBN 13: 9783659523359
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 88 pp. Englisch. Seller Inventory # 9783659523359
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Performance Optimization in Network-on-Chip (NoC) Architecture
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LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659523356
ISBN 13: 9783659523359
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques. Seller Inventory # 9783659523359
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Performance Optimization in Network-on-Chip (NoC) Architecture
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LAP LAMBERT Academic Publishing, 2014
ISBN 10: 3659523356
ISBN 13: 9783659523359
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Taschenbuch. Condition: Neu. Performance Optimization in Network-on-Chip (NoC) Architecture | Nurbaizura Ramji (u. a.) | Taschenbuch | 88 S. | Englisch | 2014 | LAP LAMBERT Academic Publishing | EAN 9783659523359 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 105435237