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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Published by
LAP LAMBERT Academic Publishing Sep 2013, 2013
ISBN 10: 365942093X
ISBN 13: 9783659420931
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Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. 84 pp. Englisch. Seller Inventory # 9783659420931
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
ISBN 10: 365942093X
ISBN 13: 9783659420931
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Softcover
Seller: Books Puddle, Woodside, NY, U.S.A.
Seller rating 4 out of 5 stars
Condition: New. Seller Inventory # 26400898688
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
ISBN 10: 365942093X
ISBN 13: 9783659420931
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Softcover
Seller: Majestic Books, Hounslow, United Kingdom
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Condition: New. Print on Demand. Seller Inventory # 395478367
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
ISBN 10: 365942093X
ISBN 13: 9783659420931
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Softcover
Seller: Biblios, Frankfurt am main, HESSE, Germany
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Condition: New. PRINT ON DEMAND. Seller Inventory # 18400898698
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Published by
LAP LAMBERT Academic Publishing, 2013
ISBN 10: 365942093X
ISBN 13: 9783659420931
New
Softcover
Seller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sharma GeetanjaliMs. Geetanjali Sharma received her Master s degree in VLSI Design and B.Tech degree in Electronics and Communication Engg. from Rajasthan University,India.She is currently working as an Assistant Professor with MSIT,. Seller Inventory # 385766639
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Published by
LAP LAMBERT Academic Publishing Sep 2013, 2013
ISBN 10: 365942093X
ISBN 13: 9783659420931
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 84 pp. Englisch. Seller Inventory # 9783659420931
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Published by
LAP LAMBERT Academic Publishing
ISBN 10: 365942093X
ISBN 13: 9783659420931
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. Seller Inventory # 9783659420931