Synopsis
In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.
"synopsis" may belong to another edition of this title.
About the Author
Received B.E. degree in E&C from MMM Engineering College, Gorakhpur, and M.Tech. in VLSI Design from MITS, Sikar. He is currently pursuing Ph.D. from SGVU, Jaipur in Low Power VLSI Device design. He has published research papers in reputed journals and conferences. He is also editorial board member and reviewer of well reputed journals.
"About this title" may belong to another edition of this title.
Search results for Low Power Latch Designs in Subthreshold Region: Designs...
Seller Image
Low Power Latch Designs in Subthreshold Region
Published by
LAP LAMBERT Academic Publishing Jun 2012, 2012
ISBN 10: 365916061X
ISBN 13: 9783659160615
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications. 80 pp. Englisch. Seller Inventory # 9783659160615
Seller Image
Low Power Latch Designs in Subthreshold Region
Published by
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 365916061X
ISBN 13: 9783659160615
New
Softcover
Seller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sharma Krishna GopalReceived B.E. degree in E&C from MMM Engineering College, Gorakhpur, and M.Tech. in VLSI Design from MITS, Sikar. He is currently pursuing Ph.D. from SGVU, Jaipur in Low Power VLSI Device design. He has published . Seller Inventory # 5135954
Buy New
£ 36.22
£ 41.97 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Seller Image
Low Power Latch Designs in Subthreshold Region
Published by
LAP LAMBERT Academic Publishing Jun 2012, 2012
ISBN 10: 365916061X
ISBN 13: 9783659160615
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 80 pp. Englisch. Seller Inventory # 9783659160615
Seller Image
Low Power Latch Designs in Subthreshold Region : Designs for Portable applications
Published by
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 365916061X
ISBN 13: 9783659160615
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications. Seller Inventory # 9783659160615
Seller Image
Low Power Latch Designs in Subthreshold Region | Designs for Portable applications
Published by
LAP LAMBERT Academic Publishing, 2012
ISBN 10: 365916061X
ISBN 13: 9783659160615
New
Taschenbuch
Seller: preigu, Osnabrück, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Low Power Latch Designs in Subthreshold Region | Designs for Portable applications | Krishna Gopal Sharma (u. a.) | Taschenbuch | 80 S. | Englisch | 2012 | LAP LAMBERT Academic Publishing | EAN 9783659160615 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Seller Inventory # 106409964