A Bit-Serial Implementation of the AES Encryption Algorithm: Implementation and Space Optimization of the Advanced Encryption Standard for a Bit-Serial Fully Pipelined Architecture - Softcover
Synopsis
In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization.
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About the Author
Raphael Weber is a research assistant at the OFFIS institute for information technology in Oldenburg, Germany. He studied computer science with minor in mechanical engineering at the University of Paderborn where he completed his diploma degree in 2009. His research interests include new hardware/software design and optimization methods.
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A Bit-Serial Implementation of the AES Encryption Algorithm
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VDM Verlag Dr. Müller, 2011
ISBN 10: 3639327136
ISBN 13: 9783639327137
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Kartoniert / Broschiert. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Weber RaphaelRaphael Weber is a research assistant at the OFFIS institute for information technology in Oldenburg, Germany. He studied computer science with minor in mechanical engineering at the University of Paderborn where he c. Seller Inventory # 4977933
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A Bit-Serial Implementation of the AES Encryption Algorithm : Implementation and Space Optimization of the Advanced Encryption Standard for a Bit-Serial Fully Pipelined Architecture
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Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization. Seller Inventory # 9783639327137
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A Bit-Serial Implementation of the AES Encryption Algorithm: Implementation and Space Optimization of the Advanced Encryption Standard for a Bit-Serial Fully Pipelined Architecture
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