Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation: 10th International Workshop, PATMOS 2000, Göttingen, Germany, ... (Lecture Notes in Computer Science, 1918) - Softcover
Synopsis
This book constitutes the refereed proceedings of the 10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Göttingen, Germany in September 2000.
The 33 revised full papers presented were carefully reviewed and selected for inclusion in the book. The papers are organized in sections on RTL power modeling, power estimation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules, and analog-digital circuit modeling.
"synopsis" may belong to another edition of this title.
Search results for Integrated Circuit Design: Power and Timing Modeling,...
Stock Image
Integrated Circuit Design Power and Timimg Modeling, Optimization and Simulation
Seller: CONTINENTAL MEDIA & BEYOND, Ocala, FL, U.S.A.
Seller rating 5 out of 5 stars
Condition: Used: Good. xlibrary paperback 2000 withdrawn stamp in book/ on edge of pages clean text 338 pages::: L-2. Seller Inventory # 0317M7WR53P
Seller Image
Integrated Circuit Design : Power and Timing Modeling, Optimization and Simulation : 10th International Workshop, Patmos 2000, Gottingen, Germany, September 13-15, 2000 proceedin
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: As New. Unread book in perfect condition. Seller Inventory # 915627
Stock Image
Integrated Circuit Design Power and Timimg Modeling, Optimization and Simulation
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In. Seller Inventory # ria9783540410683_new
Buy New
£ 50.43
£ 11.98 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Stock Image
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation: 10th International Workshop, PATMOS 2000, G??ttingen, Germany, . (Lecture Notes in Computer Science)
Seller: Chiron Media, Wallingford, United Kingdom
Seller rating 5 out of 5 stars
Paperback. Condition: New. Seller Inventory # 6666-IUK-9783540410683
Buy New
£ 48.02
£ 15.49 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 10 available
Seller Image
Integrated Circuit Design : Power and Timing Modeling, Optimization and Simulation : 10th International Workshop, Patmos 2000, Gottingen, Germany, September 13-15, 2000 proceedin
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 915627-n
Buy New
£ 50.42
£ 15 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Seller Image
Integrated Circuit Design : Power and Timing Modeling, Optimization and Simulation : 10th International Workshop, Patmos 2000, Gottingen, Germany, September 13-15, 2000 proceedin
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 915627-n
Seller Image
Integrated Circuit Design : Power and Timing Modeling, Optimization and Simulation : 10th International Workshop, Patmos 2000, Gottingen, Germany, September 13-15, 2000 proceedin
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: As New. Unread book in perfect condition. Seller Inventory # 915627
Buy Used
£ 55.88
£ 15 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Seller Image
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation
Published by
Springer Berlin Heidelberg, 2000
ISBN 10: 3540410686
ISBN 13: 9783540410683
New
Softcover
Seller: moluna, Greven, Germany
Seller rating 4 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Includes supplementary material: sn.pub/extrasOpening.- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action.- RTL Power Modeling.- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation. Seller Inventory # 4889063
Buy New
£ 43.11
£ 42.39 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Seller Image
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation
Published by
Springer Berlin Heidelberg Sep 2000, 2000
ISBN 10: 3540410686
ISBN 13: 9783540410683
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Thisworkshopisthetenthinaseriesofinternationalworkshops. Thisyear ittakesplaceinG ottingen,Germany,andisorganizedbytheUniversityof Hannover. G ottingenhasonethemostfamousGermanuniversities,whereverywell knownscientistslikeLichtenberg,Hilbert,GaussandvonNeumannstudied, workedandtaught. ItalsohostsseveralresearchinstitutesoftheMax-Planck- Society. The rstelectronictubecalculatorG1wasbuiltinG ottingenin1952 byH. Billing. Additionally,G ottingenwasselectedbecauseitisadjacenttothe worldexpositionEXPO2000inHannoverwhichgivesanoutlookintothe21st centurycoveringthemajortopicsofhumankind,natureandtechnology. WithrespecttotheseinspiringsurroundingsthetechnicalprogramofPAT- MOS2000includes10sessionsdedicatedtomostimportantsubjectsofpower andtimingmodeling,optimizationandsimulationatthedawnofthe21stc- tury. ThefourinvitedtalksaddresstheEuropeanresearchactivitiesinthewo- shop elds,theevolvingneedsforminimalpowerconsumptionintheareaof wirelessandchipcardapplicationsanddesignmethodologiesofveryhighly- tegratedmultimediaprocessors. Theworkshopisaresultofthejointworkofalargenumberofindividuals, whocannotallbementionedhere. Inparticular,wewouldliketoacknowledge theoutstandingworkofthereviewers,whodidacompetentjobinatimely manner. Wealsohavetothankthemembersofthelocalorganizingcommittee fortheire ortinenablingtheconferencetorunsmoothly. Finally,wegratefully acknowledgethesupportofallorganizationsandinstitutionssponsoringthe conference. September2000 PeterPirsch ErichBarke DimitriosSoudris Organization OrganizationCommitee GeneralCoChairs: PeterPirsch(UniversityofHannover,Germany) ErichBarke(UniversityofHannover,Germany) ProgramChair: DimitriosSoudris (DemocritusUniversityofThrace,Greece) FinanceChair: LarsHedrich(UniversityofHannover,Germany) PublicationChair: AchimFreimann (UniversityofHannover,Germany) Audio-VisualChair: J orgAbke(UniversityofHannover,Germany) LocalArrangementsChair: CarstenReuter(UniversityofHannover,Germany) ProgramCommitee D. Auvergne(UniversityofMontpellier,France) J. Bormans(IMEC,Belgium) J. Figueras(UniversityofCatalunya,Spain) C. E. Goutis(UniversityofPatras,Greece) A. Guyot(INPGGrenoble,France) R. Hartenstein(UniversityofKaiserslautern,Germany) S. Jones(UniversityofLoughborough,UnitedKingdom) P. Larsson-Edefors(UniversityofLink oping,Sweden) E. Macii(PolytechnicofTorino,Italy) V. Moshnyaga(UniversityofFukuoka,Japan) W. Nebel(UniversityofOldenburg,Germany) J. A. Nossek(TechnicalUniversityofMunc hen,Germany) A. Nunez(UniversityofLasPalmas,Spain) M. Papaefthymiou(UniversityofMichigan,UnitedStates) M. Pedram(UniversityofSouthernCalifornia,UnitedStates) H. P eiderer(UniversityofUlm,Germany) C. Piguet(CSEM,Switzerland) R. Reis(UniversityofPortoAlegre,Brazil) M. Robert(UniversityofMontpellier,France) A. Rubio(UniversityofCatalunya,Spain) J. Sparsĝ(TechnicalUniversityofDenmark,Denmark) A. Stempkowsky(AcademyofSciences,Russia) T. Stouraitis(UniversityofPatras,Greece) J. F. M. Theeuwen(Philips,TheNetherlands) A. -M. Trullemans-Anckaert(UniversityofLouvain,Belgium) R. Zafalon(STMicroelectronics,Italy) VIII Organization SteeringCommitee D. Auvergne(UniversityofMontpellier,France) R. Hartenstein(UniversityofKaiserslautern,Germany) W. Nebel(UniversityofOldenburg,Germany) C. Piguet(CSEM,Switzerland) A. Rubio(UniversityofCatalunya,Spain) J. Sparsĝ(TechnicalUniversityofDenmark,Denmark) A. -M. Trullemans-Anckaert(UniversityofLouvain,Belgium) SponsoringInstitutions EuropeanCommissionDirectorate GeneralInformationSociety IEEECircuitsandSystemsSociety TableofContents Opening Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 R. vanLeuken,R. Nouta,A. deGraf(DelftUniversityofTechnology, TheNetherlands) RTL Power Modeling Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. . . . . . . . . . . . . . . . . . 3 M. Anton,M. Chinosi,D. Sirtori,R. Zafalon(STMicroelectronics, Italy) Power Models for Semi-autonom 356 pp. Englisch. Seller Inventory # 9783540410683
Seller Image
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation
Published by
Springer, Springer Sep 2000, 2000
ISBN 10: 3540410686
ISBN 13: 9783540410683
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Opening.- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action.- RTL Power Modeling.- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.- Power Models for Semi-autonomous RTL Macros.- Power Macro-Modelling for Firm-Macro.- RTL Estimation of Steering Logic Power.- Power Estimation and Optimization.- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.- Framework for High-Level Power Estimation of Signal Processing Architectures.- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions.- System-Level Design.- A Holistic Approach to System Level Energy Optimization.- Early Power Estimation for System-on-Chip Designs.- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.- Transistor-Level Modeling.- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design.- Impact of Voltage Scaling on Glitch Power Consumption.- Degradation Delay Model Extension to CMOS Gates.- Second Generation Delay Model for Submicron CMOS Process.- Asynchronous Circuit Design.- Semi-modular Latch Chains for Asynchronous Circuit Design.- Asynchronous First-in First-out Queues.- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance.- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.- Power Efficient Technologies.- Low Power Design Techniques for Contactless Chipcards.- Dynamic Memory Design for Low Data-Retention Power.- Double-Latch Clocking Scheme for Low-Power I.P. Cores.- Design of Multimedia Processing Applications.- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip.- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder.- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.- AdiabaticDesign and ArithmeticModules.- Design of Reversible Logic Circuits by Means of Control Gates.- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.- An Adiabatic Multiplier.- Logarithmic Number System for Low-Power Arithmetic.- Analog-Digital Circuits Modeling.- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.- PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 356 pp. Englisch. Seller Inventory # 9783540410683