Realization of Memory Fault Tolerance using Error Correcting Codes - Softcover

S. Murti Sarma, N.; Lavanya, Poluboyina; Prasad Acharya, Gobinda

Softcover

ISBN 10: 3330044195 ISBN 13: 9783330044197

Publisher: LAP LAMBERT Academic Publishing, 2017

Synopsis

This work is aimed towards the implementation of a fault-tolerant memory system with the help of supporting circuits. This work demonstrates an improvement on the reliability of a semiconductor memory system using Error control codes (ECC)and Low Density Parity Check (LDPC) Codes as a part of protecting support logic. It is observed that the error correcting codes with higher hamming distances can detect more errors i.e. as higher the hamming distance higher the error control capability.

About this title

About the Author

Asst.Prof.Poluboyina Lavanya and Assoc.Prof.Gobinda Prasad Acharya are upgrowing research scholars of JNTUK and JNTUH in the areas of wireless networks and VLSI testing respectively. N S Murti Sarma together with above are faculty of Sreenidhi Institute of Science and Technology. All the authors of the book are with significant credits of research.

Edition details

• Publisher: LAP LAMBERT Academic Publishing
• Publication date: 2017
• Language: English
• ISBN 10: 3330044195
• ISBN 13: 9783330044197
• Binding: Paperback
• Number of pages: 128