IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection (Analog Circuits and Signal Processing) - Softcover

Mohamed, Khaled Salah

Softcover

ISBN 10: 3319373587 ISBN 13: 9783319373584

Publisher: Springer, 2016

Synopsis

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies.

Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;

Introduce a deep introduction for Verilog for both implementation and verification point of view.

Demonstrates how to use IP in applications such as memory controllers and SoC buses.

Describes a new verification methodology called bug localization;

Presents a novel scan-chain methodology for RTL debugging;

Enables readers to employ UVM methodology in straightforward, practical terms.

About this title

About the Author

Dr. Khaled Salah attended the school of engineering, Department of Electronics and Communications at Ain-Shams University, Egypt, from 1998 to 2003, where he received his B.Sc. degree in Electronics and Communications Engineering with distinction and honor degree. He received his M.Sc. and his Ph.D. degrees in Electronics and Communications in 2008, 2012 respectively. He joined Mentor Graphic Corporation, where he designed many SoC IPs such as AHB, HDMI, HDCP, eMMC, SDcard, HMC. Currently, Dr. Khaled Salah is a Technical Lead at the Emulation division at Mentor Graphic, Egypt. Dr. Khaled Salah has published one book and more than 42 research papers in the top refereed journals and conferences. His research interests are in 3D integration, IP Modeling, and SoC design.

From the Back Cover

This book describes the life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection. Various trade-offs in the design process are discussed, including those associated with many of the most common memory cores, controller IPs and system-on-chip (SoC) buses. Readers will also benefit from the author’s practical coverage of new verification methodologies. such as bug localization, UVM, and scan-chain. A SoC case study is presented to compare traditional verification with the new verification methodologies.

· Discusses the entire life cycle process of IP cores, from specification to production, including IP modeling, verification, optimization, and protection;

· Introduce a deep introduction for Verilog for both implementation and verification point of view.

· Demonstrates how to use IP in applications such as memory controllers and SoC buses.

· Describes a new verification methodology called bug localization;

· Presents a novel scan-chain methodology for RTL debugging;

· Enables readers to employ UVM methodology in straightforward, practical terms.

Edition details

• Publisher: Springer
• Publication date: 2016
• Language: English
• ISBN 10: 3319373587
• ISBN 13: 9783319373584
• Binding: Paperback
• Number of pages: 163