This book provides readers with an overview of the fundamental definitions and features of Multiple-Valued Logic (MVL). The authors include a brief discussion of the historical development of MVL technologies, while the main goal of the book is to present a comprehensive review of different technologies that are being explored to implement multiple-valued or beyond-binary memory circuits and systems. The discussion includes the basic features, prospects, and challenges of each technology, while highlighting the significant works done on different branches of MVL memory architecture, such as sequential circuits, random access memory, Flash memory, etc.
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Zarin T. Sandhie received the B.Sc degree in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET), Dhaka, Bangladesh in 2015. She received her M.S. and Ph.D. degree in Electrical and Computer Engineering from University of Missouri-Kansas City in 2020 and 2021 respectively. She authored ~10 research publications during her M.S. and Ph.D. research. Her research interests include Multiple-Valued Logic (MVL), ternary logic, and Graphene-Nano-Ribbon Field Effect Transistor (GNRFET). Zarin was awarded the UMKC School of Graduate Studies Research Grant in 2018. She got the 1st prize in UMKC hack-a-roo 2018. She completed her internship as a graduate intern at Intel in the Atom CPU Design Team. Currently she is working as SoC Design Engineer in the IPG group in Intel Corporation.
This book provides readers with an overview of the fundamental definitions and features of Multiple-Valued Logic (MVL). The authors include a brief discussion of the historical development of MVL technologies, while the main goal of the book is to present a comprehensive review of different technologies that are being explored to implement multiple-valued or beyond-binary memory circuits and systems. The discussion includes the basic features, prospects, and challenges of each technology, while highlighting the significant works done on different branches of MVL memory architecture, such as sequential circuits, random access memory, Flash memory, etc.
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