This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches
• interrupts and exceptions
• memory management units (MMUs)• pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
"synopsis" may belong to another edition of this title.
This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.
It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:
• MIPS instruction set architecture (ISA) for application and for system programming
• cache coherent memory system
• store buffers in front of the data caches• interrupts and exceptions
• memory management units (MMUs)
• pipelined processors: the classical five-stage pipeline is extended by two pipeline
stages for address translation
• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)
• I/O-interrupt controller and a disk
"About this title" may belong to another edition of this title.
Seller: Brook Bookstore On Demand, Napoli, NA, Italy
Condition: new. Questo è un articolo print on demand. Seller Inventory # ef5ae6d6b666b5f4b8f7e7076fe04cc6
Quantity: Over 20 available
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: New. Seller Inventory # 41448405-n
Seller: California Books, Miami, FL, U.S.A.
Condition: New. Seller Inventory # I-9783030432423
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Condition: As New. Unread book in perfect condition. Seller Inventory # 41448405
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Condition: New. In. Seller Inventory # ria9783030432423_new
Quantity: Over 20 available
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Condition: New. Seller Inventory # 41448405-n
Quantity: Over 20 available
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This work is building on results from the book named 'A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness' by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:- MIPS instruction set architecture (ISA) for application and for system programming- cache coherent memory system- store buffers in front of the data caches- interrupts and exceptions- memory management units (MMUs)- pipelined processors: the classical five-stage pipeline is extended by two pipelinestages for address translation- local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)- I/O-interrupt controller and a disk 644 pp. Englisch. Seller Inventory # 9783030432423
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Condition: As New. Unread book in perfect condition. Seller Inventory # 41448405
Quantity: Over 20 available
Seller: Kennys Bookshop and Art Galleries Ltd., Galway, GY, Ireland
Condition: New. Seller Inventory # V9783030432423
Seller: Books Puddle, New York, NY, U.S.A.
Condition: New. pp. 628. Seller Inventory # 26376874595