Synopsis
Engineers face stiff challenges in designing phase-locked loop (PLL) circuits for wireless communications thanks to phase noise and other obstacles. This practical book comes to the rescue with a proven PLL design and optimization methodology that lets designers assess their options, predict PLL behavior, and develop cost-effective PLLs that meet performance requirements no matter what IC (integrated circuit) challenges they come up against. This uniquely comprehensive toolkit takes designers step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. It provides a sample design of a fully integrated PLL for WLAN applications, demonstrating every step from specs definition and circuit characterization to layout generation and circuit schematics.
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About the Author
Guillermo Bistue is a researcher at The Centro de Estudios e Investigaciones Tecnicas de Gipuzkoa (CEIT) in Navarro, Spain. He received his M.Sc. and Ph.D. degrees from the Engineering School of the University of Navarra. Inigo Adin is a researcher at The Centro de Estudios e Investigaciones Tecnicas de Gipuzkoa (CEIT) in Navarro, Spain. He received his M.Sc. in Electronics Engineering and his Ph.D. at the University of Navarra. Carlos Quemada is a researcher with IKERLAN, Mondragon, Spain. He has published several papers in the field of CMOS technology and was previously a member of the Engineering Faculty at the University of Navarra. He earned his M.Sc. in telecommunications engineering and his Ph.D. in industrial engineering, both at the University of Navarra.
"About this title" may belong to another edition of this title.
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Design Methodology for RF CMOS Phase Locked Loops
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Artech House Publishers, 2009
ISBN 10: 1596933836
ISBN 13: 9781596933835
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INTEGRATED PHASE LOCK LOOPS FOR HIGH FREQUENCY WIRELESS COMMUNICATIONS SYSTEMS
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INTEGRATED PHASE LOCK LOOPS FOR HIGH FREQUENCY WIRELESS COMMUNICATIONS SYSTEMS
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Design Methodology for RF CMOS Phase Locked Loops
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Design Methodology for RF CMOS Phase Locked Loops
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Design Methodology for RF CMOS Phase Locked Loops
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