Formal Semantics and Proof Techniques for Optimizing VHDL Models - Softcover

Umamageswaran, Kothanda; Pandey, Sheetanshu L.; Wilsey, Philip A.

 
9781461551249: Formal Semantics and Proof Techniques for Optimizing VHDL Models
Softcover
ISBN 10: 1461551242 ISBN 13: 9781461551249
Publisher: Springer, 2011

This specific ISBN edition is currently not available.

Synopsis

1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.

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Publisher
Springer
Publication date
2011
Language
English
ISBN 10 
1461551242
ISBN 13 
9781461551249
Binding
Paperback

Other Popular Editions of the Same Title

9780792383758: Formal Semantics and Proof Techniques for Optimizing VHDL Models

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ISBN 10:  0792383753 ISBN 13:  9780792383758
Publisher: Springer, 1998
Hardcover