The e Hardware Verification Language (Information Technology: Transmission, Processing & Storage) - Hardcover

Iman, Sasan; Joshi, Sunita

Hardcover

ISBN 10: 1402080239 ISBN 13: 9781402080234

Publisher: Springer, 2004

Synopsis

I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.

About this title

Product Description

The E-Hardware Verification Language Covers the e-hardware verification language (HVL), state of the art in verification methodologies, and the use of eHVL as a facilitating verification tool in implementing a state of the art verification environment. This book describes the fresh concepts introduced by the e-language, e-language syntax, and its associated semantics.

Synopsis

This book provides a detailed coverage of the e-hardware verification language (HVL), state of the art in verification methodologies, and the use of eHVL as a facilitating verification tool in implementing a state of the art verification environment. To this end, the book provides a comprehensive description of the new concepts introduced by the e-language, e-language syntax, and its associated semantics. In addition, the book describes architectural views and requirements of verification environments (i.e. randomly generated environments, coverage driven verification environments, etc.). Verification blocks in the architectural views (i.e. Generators, Initiators, Collectors, Checkers, Monitors, Coverage Definitions, etc.) and their implementations using the eHVL are also discussed in detail in separate parts of the book. The book describes the eReuse Methodology (RM), the motivation for defining such a guideline and step-by-step instructions for building an eRM compliant eVerification Component (eVC). A complete implementation of a UART eRM compliant eVC is used as the working example for putting all topics in perspective.

This book is useful for a range of users, including junior verification engineers looking to learn just enough basic concepts and related syntax to get a head start on their project, advance users looking to enhance the effectiveness and quality of a verification environment, developers working to build eVerification Components and finally as reference for looking up specific information about a verification concept and its implementation using the eHVL.

Edition details

• Publisher: Springer
• Publication date: 2004
• Language: English
• ISBN 10: 1402080239
• ISBN 13: 9781402080234
• Binding: Hardcover
• Number of pages: 371