Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms - Hardcover

Kogel, Tim; Leupers, Rainer; Meyr, Heinrich

Hardcover

ISBN 10: 1402048254 ISBN 13: 9781402048258

Publisher: Springer, 2006

Synopsis

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

About this title

Review

From the reviews:

"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool ... . This book’s scope and range of pragmatic ideas make it valuable for a wide audience. ... When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area ... . It should resonate with students, researchers, and practical designers ... ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)

Synopsis

The drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification. In response to the vast complexity of heterogeneous multi-processor platforms, the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models. "Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms" first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction.

Subsequently, this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

Edition details

• Publisher: Springer
• Publication date: 2006
• ISBN 10: 1402048254
• ISBN 13: 9781402048258
• Binding: Hardcover
• Language: English
• Number of pages: 200