A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications - Softcover

Hunt, Bruce W

Softcover

ISBN 10: 1249584248 ISBN 13: 9781249584247

Publisher: Biblioscholar, 2012

Synopsis

A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed bya discussion of circuit design parameters; specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16-point FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.

Edition details

• Publisher: Biblioscholar
• Publication date: 2012
• Language: English
• ISBN 10: 1249584248
• ISBN 13: 9781249584247
• Binding: Paperback
• Number of pages: 130