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Synopsis
This manual has been specifically written for hardware designers that use the Verilog or VHDL hardware description languages to design complex integrated circuits. Whether a designer designs individual circuit modules or complete systems, designers are always faced with the problem of ensuring that the final design is completely free of errors. Achieving design-quality while satisfying budget and time constraints is one of the major objectives for designers in the 21st century. The manual lays the foundation for a methodology based on the effective use of the following front-end design tools and validation techniques. Code and rule checking; Property checking; Code and FSM coverage analysis; Test suite analysis; System verification; The manual includes numerous examples of front-end verification techniques using leading-edge HDL verification tools supplied by TransEDA (one of the world's foremost EDA tool vendors). The manual contains a number of case studies and worked examples that together with evaluation copies of TransEDA's verification tools may be downloaded from the World Wide Web for evaluation purposes.
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Verification Methodology Manual: Techniques for Verifying HDL Designs
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Verification Methodology Manual: Techniques for Verifying HDL Designs
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Condition: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear. Seller Inventory # GWSVV.0953848221.G
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