Items related to VLSI Fault Modeling and Testing Techniques (VLSI Design...
Synopsis
VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.
"synopsis" may belong to another edition of this title.
About the Author
brist /f George /i W.
"About this title" may belong to another edition of this title.
Search results for VLSI Fault Modeling and Testing Techniques (VLSI Design...
Stock Image
VLSI Fault Modeling and Testing Techniques
Print on DemandSeller: PBShop.store UK, Fairford, GLOS, United Kingdom
Seller rating 5 out of 5 stars
HRD. Condition: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # L1-9780893917814
Buy New
£ 67.07
£ 4.16 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Seller Image
Vlsi Fault Modeling and Testing Techniques
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 823827-n
Stock Image
VLSI Fault Modeling and Testing Techniques
Print on DemandSeller: PBShop.store US, Wood Dale, IL, U.S.A.
Seller rating 5 out of 5 stars
HRD. Condition: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Seller Inventory # L1-9780893917814
Seller Image
Vlsi Fault Modeling and Testing Techniques
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: As New. Unread book in perfect condition. Seller Inventory # 823827
Seller Image
VLSI Fault Modeling and Testing Techniques (Hardcover)
Published by
Bloomsbury Publishing Plc, Westport, 1993
ISBN 10: 0893917818
ISBN 13: 9780893917814
New
Hardcover
Seller: Grand Eagle Retail, Bensenville, IL, U.S.A.
Seller rating 5 out of 5 stars
Hardcover. Condition: new. Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9780893917814
Stock Image
VLSI Fault Modeling and Testing Techniques: (VLSI Design Automation Series)
Seller: California Books, Miami, FL, U.S.A.
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # I-9780893917814
Seller Image
Vlsi Fault Modeling and Testing Techniques
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 823827-n
Buy New
£ 67.06
£ 15 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Seller Image
Vlsi Fault Modeling and Testing Techniques
Seller: GreatBookPricesUK, Woodford Green, United Kingdom
Seller rating 5 out of 5 stars
Condition: As New. Unread book in perfect condition. Seller Inventory # 823827
Buy Used
£ 72.60
£ 15 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Stock Image
Vlsi Fault Modeling and Testing Techniques
Seller: Revaluation Books, Exeter, United Kingdom
Seller rating 5 out of 5 stars
Hardcover. Condition: Brand New. 208 pages. 9.50x6.50x0.75 inches. In Stock. Seller Inventory # x-0893917818
Buy New
£ 94.49
£ 10 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 2 available
Stock Image
VLSI Fault Modeling and Testing Techniques (Hardcover)
Published by
Bloomsbury Publishing Plc, Westport, 1993
ISBN 10: 0893917818
ISBN 13: 9780893917814
New
Hardcover
Seller: CitiRetail, Stevenage, United Kingdom
Seller rating 5 out of 5 stars
Hardcover. Condition: new. Hardcover. VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. This text explores VLSI fault modelling and testing techniques and covers such topics as: physical fault modelling and simulation for VSLI MOS circuits; designing CMOS gates to test open faults; testing bridging faults in VLSI; and testable design synthesis models. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability. Seller Inventory # 9780893917814
Buy New
£ 71.99
£ 37 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 1 available