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Synopsis
An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright Book News, Inc. Portland, Or.
"synopsis" may belong to another edition of this title.
Synopsis
An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield project
"About this title" may belong to another edition of this title.
- PublisherIEEE Publications,U.S.
- Publication date1995
- ISBN 10 0818671076
- ISBN 13 9780818671074
- BindingHardcover
- LanguageEnglish
- Number of pages305
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The IEEE international workshop on Defect & Fault-Tolerance in VLSI Systems, Proceedings, 1995.
Published by
IEEE Computer Society Press, Los Alamitos, 1995
ISBN 10: 0818671076
ISBN 13: 9780818671074
Used
Hardcover
Seller: Lost and Found Books, Healesville, VIC, Australia
Seller rating 5 out of 5 stars
hard cover. No Jacket. Illustrated in black and white. 305 pages VG. Slight shelf wear to covers, overall very good condition. Seller Inventory # 13953
Quantity: 1 available