Synopsis
Synthesizes recent findings on the chance of missing a faulty circuit when the data from testing microelectronic systems is compacted to be more manageable, a situation known as aliasing. Considers single and multiple stuck-at, delay, and stuck-open faults. Also reviews the testing of VLSI, introduces some common linear compactors, presents two definitions of aliasing probability, and discusses probabilistic fault models and their practical validity. No index. Annotation copyright Book News, Inc. Portland, Or.
"synopsis" may belong to another edition of this title.
Synopsis
Synthesizes recent findings on the chance of missing a faulty circuit when the data from testing microelectronic systems is compacted to be more manageable, a situation known as aliasing. Considers single and multiple stuck-at, delay, and stuck-open faults. Also reviews the testing of VLSI, introduces some common linear compactors, presents two def
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A Probabilistic Analysis of Test Response Compaction
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Condition: Good. [ No Hassle 30 Day Returns ][ Ships Daily ] [ Underlining/Highlighting: NONE ] [ Writing: NONE ] [ Edition: first ] Publisher: Institute of Electrical & Electronics Enginee Pub Date: 3/1/1995 Binding: Paperback Pages: 95 first edition. Seller Inventory # 5848608
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A Probabilistic Analysis of Test-Response Compaction
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Institute of Electrical & Electr, 1995
ISBN 10: 0818665327
ISBN 13: 9780818665325
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