Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems - Hardcover

Thoen, Filip; Catthoor, Francky

Hardcover

ISBN 10: 0792377370 ISBN 13: 9780792377375

Publisher: Springer, 1999

Synopsis

system is a complex object containing a significant percentage of elec­ A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro­ processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten­ ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge­ neous and contain almost always programmable components.

About this title

Synopsis

The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical revolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging "systems-on-a-chip" (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modelling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. This text gives a comprehensive overview of existing techniques. The emphasis throughout is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market.

The proposed "Multi-Thread Graph" (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects ("timeliness"), while minimizing processor cost overhead as driven by high-level cost estimators. The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by coestimators, selects the scheduling policy for each behaviour. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component.

The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints.

Edition details

• Publisher: Springer
• Publication date: 1999
• ISBN 10: 0792377370
• ISBN 13: 9780792377375
• Binding: Hardcover
• Language: English
• Number of pages: 453