VLSI Planarization: Methods, Models, Implementation: 399 (Mathematics and Its Applications, 399) - Hardcover

Feinberg, V.Z.; Levin, A.G.; Rabinovich, E.B.

Hardcover

ISBN 10: 079234510X ISBN 13: 9780792345107

Publisher: Springer, 1997

Synopsis

At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun­ nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer­ aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.

About this title

Review

`Altogether, the book is very well written and a good piece of work. All the notions are clearly defined and the proofs are presented in detail. Many pictures illustrate the subjects discussed and help to make things clear and understandable.'
Mathematical Reviews, 98m

Synopsis

VLSI planarization is one of the basic stages of the so-called topological approach to VLSI design. This text considers the intense recent development in this field. Although it features an analysis of the problem and the results of different authors are classified and generalized, this volume is mainly based on the investigations conducted by the present authors during the last fifteen years. This included work in the field of design and research in mathematical methods applied to the mentioned approach for computer-aided design, and in the field of designing concrete industrial design systems. The theory and methods discussed here may be applied to printed-circuit boards, hybrid circuits, etc. This work concentrates on "essentially" hypergraph models of electric circuits and their planarization techniques. It is just this aspect of the topological approach to design that has not been adequately investigated before.

Edition details

• Publisher: Springer
• Publication date: 1997
• Language: English
• ISBN 10: 079234510X
• ISBN 13: 9780792345107
• Binding: Hardcover
• Number of pages: 192