Formal Very Large Scale Integration Specification and Synthesis (v. 1) (Very Large Scale Integration Design Methods: International Workshop Proceedings) - Hardcover
Synopsis
Functional and behavioral verification of correctness forms the bottleneck in current VLSI design systems. For economical reasons, design of VLSI circuits must be completely validated before manufacturing. Current VLSI validation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods that guarantee correctness. This book describes original work in all aspects of formal hardware design methods. Topics covered include high-level specification, hardware description languages, formal hardware verification methods, guided synthesis methods, correctness preserving transformations, use of theorem provers for verification, formal proof of correctness, MOS timing verification methods, design for verifiability, and practical experiences.
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Formal VLSI Specification and Synthesis: VLSI Design Methods (2 Volume Set)
Published by
Elsevier Science Publishers, 1990
ISBN 10: 0444886893
ISBN 13: 9780444886897
Used
Hardcover
Seller: Crossroad Books, Eau Claire, WI, U.S.A.
Seller rating 5 out of 5 stars
Hardcover. Condition: with no dust jacket. Dust Jacket Condition: No Dust Jacket. Two Volume Set. Ex-Corporate Library copy; with typical markings. Library label on front board and on spine tail. Spine twists. Pages clean, but for library markings. This is a fairly heavy set; Priority and/or International may require shipping over and above standard costs. ; TEH22A; Ex-Library. Seller Inventory # 57066